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suisuisi
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SUISUISI
@suisuisi
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Open GitHub
null
OpenFPGA
Profile age: about 9 years
Updated 7 days ago
0 followers • 0 following
Contacts
zhulikun2011@126.com
Repositories
FPGAandCNN
346
73
updated over 2 years ago • age almost 4 years
Verilog
65.7%
Python
19.9%
C++
9.1%
HTML
2.9%
SystemVerilog
2.4%
FPGA_Library
228
52
updated about 1 year ago • age over 2 years
VHDL
50.3%
Ada
17.1%
Verilog
13.9%
C
9.6%
C++
9.1%
FPGA
127
100
updated over 5 years ago • age about 6 years
VHDL
75.4%
Coq
18.4%
SystemVerilog
2.7%
V
2.3%
Verilog
1.2%
FPGAandImage
115
28
updated about 4 years ago • age over 4 years
VHDL
75.2%
Verilog
19.6%
SystemVerilog
2.6%
V
2.3%
Shell
0.2%
FPGAandGames
75
18
updated over 3 years ago • age over 3 years
VHDL
52.6%
C
22.9%
Verilog
12.7%
SystemVerilog
10.1%
HTML
1.6%
FPGAandUSB3.0
72
17
updated almost 4 years ago • age almost 4 years
VHDL
73.6%
Verilog
21.1%
V
3.1%
SystemVerilog
1.9%
Shell
0.2%
FPGATechnologyGroup
51
22
updated 22 days ago • age over 2 years
Verilog
47.4%
VHDL
43.4%
Shell
5.8%
SystemVerilog
1.9%
C
1.5%
FPGAandPeripheralInterface
40
24
updated over 4 years ago • age over 4 years
Verilog
61.8%
VHDL
24.6%
C
9.2%
Tcl
2.3%
Assembly
2.1%
basic_systemverilog
37
11
updated over 3 years ago • age over 3 years
Verilog
56.3%
VHDL
19.6%
HTML
12.7%
SystemVerilog
7.3%
V
4.1%
FPGAandLAN
28
23
updated over 4 years ago • age over 4 years
VHDL
59.9%
HTML
18.0%
Verilog
14.0%
C
6.2%
V
1.8%
Show more - 10 of 19 shown
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