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@stnolting
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🇪🇺 European Union
@fraunhofer-ims
Profile age: about 9 years
Updated 14 days ago
370 followers • 76 following
Repositories
neorv32
1,905
293
46
updated 7 days ago • age over 5 years
VHDL
49.2%
C
46.8%
Makefile
2.3%
Tcl
1.1%
Assembly
0.6%
neo430
Archived
204
28
3
updated almost 4 years ago • age almost 9 years
VHDL
38.4%
C
36.6%
Makefile
23.2%
Stata
0.9%
Assembly
0.9%
neoTRNG
204
25
5
updated 2 months ago • age almost 4 years
VHDL
100.0%
fpga_puf
Archived
135
22
1
updated about 3 years ago • age almost 4 years
VHDL
48.1%
C
44.0%
Makefile
7.9%
riscv-gcc-prebuilt
Archived
106
13
3
updated 9 months ago • age almost 5 years
Shell
100.0%
captouch
Archived
102
10
1
updated over 3 years ago • age about 4 years
VHDL
100.0%
neorv32-verilog
100
17
updated 11 days ago • age about 3 years
VHDL
47.5%
Verilog
34.2%
Makefile
11.9%
Shell
6.3%
neorv32-setups
84
33
updated 17 days ago • age almost 4 years
VHDL
73.7%
Tcl
14.2%
TeX
4.8%
Makefile
4.1%
Verilog
3.2%
neorv32-riscof
34
9
updated 11 days ago • age about 3 years
Python
54.9%
VHDL
35.9%
Shell
5.5%
Makefile
3.7%
fpga_torture
Archived
31
4
1
updated about 3 years ago • age about 4 years
VHDL
100.0%
Show more - 10 of 17 shown
Contributions
2025
tinyHLS
1 PR
+6
-0
Python
12
2
4
riscv_lab
~6 PRs
+473
-448
Tcl
4
0
2024
riscv-arch-test
2 PRs
+86
-83
Assembly
601
243
79
2023
airisc_core_complex
2 PRs
+60
-11
Verilog
97
20
3
2022
litex
1 PR
+60
-2
C
3,601
663
3
airisc_core_complex
~10 PRs
+143
-57
Verilog
97
20
3
2021
riscv-cores-list
1 PR
+1
-1
899
213
2020
riscv-isa-manual
1 PR
+1
-0
TeX
4,348
771
373
riscv-cores-list
2 PRs
+3
-2
899
213
