Omkar Bhilare

2022
sra-vjti.github.io
1 PR +4-4
JavaScript
29
38
2021
gsoc-proposals-archive
1 PR +0-0
478
119
litex-boards
1 PR +232-0
Python
439
333
BeagleBoard-DeviceTrees
1 PR +409-25
C
72
70
BeagleWire
2 PRs +13,823-1,990
Verilog
11
3
2020
Wall-E
1 PR +32-14
C
93
86
sra-board-component
2 PRs +14-12
C
39
24

Omkar Bhilare

@ombhilare999

Open GitHub

🇮🇳 mumbai

@BeagleWire @PyFive-RISC-V @SRA-VJTI

Profile age: over 7 years

Updated 5 days ago

105 followers • 89 following

Contacts

ombhilare999@gmail.com

https://ombhilare999.github.io

@ombhilare999

Organizations

Repositories

riscv-core

updated over 4 years ago • age almost 5 years

Verilog100.0%

vga-interface-with-TANG-PRIMER-FPGA

updated over 4 years ago • age over 4 years

Verilog94.4%

Perl5.6%

8-bit-computer

updated over 5 years ago • age over 5 years

Omni-wheel-bot-in-coppeliasim

updated over 5 years ago • age over 5 years

Zener

updated over 4 years ago • age over 4 years

Aqua_Farm_Monitor

updated over 4 years ago • age over 4 years

C++100.0%

Microchip-Discovery-kit

updated about 1 year ago • age over 1 year

HTML50.2%

Verilog47.2%

Roff1.7%

Tcl0.7%

Stata0.2%

BeagleWire

updated about 4 years ago • age over 4 years

Verilog93.5%

C5.7%

Shell0.6%

Makefile0.2%

8-Bit-ALU-implementation-on-CYCLONE-2

updated almost 5 years ago • age about 5 years

Verilog65.7%

Stata34.3%

Contributions

2022
sra-vjti.github.io
1 PR +4-4
JavaScript
29
38
2021
gsoc-proposals-archive
1 PR +0-0
478
119
litex-boards
1 PR +232-0
Python
439
333
BeagleBoard-DeviceTrees
1 PR +409-25
C
72
70
BeagleWire
2 PRs +13,823-1,990
Verilog
11
3
2020
Wall-E
1 PR +32-14
C
93
86
sra-board-component
2 PRs +14-12
C
39
24