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mmicko
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Miodrag Milanović
@mmicko
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Open GitHub
🇷🇸 Novi Sad, Serbia
Profile age: over 12 years
Updated 1 day ago
200 followers • 40 following
Contacts
mmicko@gmail.com
@micko_mame
Organizations
Repositories
prjtang
88
12
updated almost 3 years ago • age almost 7 years
C++
75.3%
Python
19.7%
CMake
3.7%
Verilog
0.8%
Tcl
0.6%
fpga101-workshop
76
15
1
updated over 6 years ago • age over 7 years
C
79.7%
Verilog
15.0%
C++
3.7%
Python
0.9%
Makefile
0.7%
enigmaFPGA
29
3
updated over 6 years ago • age about 8 years
Verilog
57.5%
Python
21.6%
C++
13.5%
Makefile
7.4%
cross-fpga
21
2
updated over 4 years ago • age about 7 years
Dockerfile
53.7%
Shell
38.8%
CMake
7.5%
grom8
20
4
updated almost 8 years ago • age almost 8 years
C++
93.6%
Verilog
5.9%
Makefile
0.5%
mikrobus-upduino
18
2
updated over 7 years ago • age over 7 years
Verilog
89.4%
C
8.2%
Assembly
1.5%
Makefile
1.0%
s100fpga
10
1
updated over 7 years ago • age over 7 years
Verilog
99.1%
Makefile
0.9%
anlogic_yosys
10
1
updated almost 7 years ago • age almost 7 years
Verilog
100.0%
workshop_badge
9
2
updated over 7 years ago • age over 7 years
Verilog
80.4%
Makefile
19.6%
VeriEMU
7
0
updated over 7 years ago • age over 7 years
C++
97.9%
C
1.0%
Lua
0.7%
Scala
0.2%
Python
0.2%
Show more - 10 of 17 shown
Contributions
2025
yosys
2 PRs
+54
-14
C++
4,053
989
57
litex
~6 PRs
+11
-3
C
3,522
647
2
nextpnr
1 PR
+24
-25
C++
1,526
270
9
oss-cad-suite-build
1 PR
+4
-4
Shell
1,159
98
1,000
linux-on-litex-vexriscv
2 PRs
+30
-0
Python
655
198
litedram
1 PR
+9
-0
Python
438
127
litex-boards
3 PRs
+527
-0
Python
429
332
yosys-slang
2 PRs
+19
-0
C++
165
29
riscv-formal
1 PR
+25
-0
Verilog
150
35
eqy
2 PRs
+14
-5
C++
46
8
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