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/louisliuwei

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Louis

@louisliuwei

🇨🇳 Shanghai

Anlogic

Profile age: over 8 years

Updated 3 days ago

66 followers • 7 following

Repositories

166

61

updated almost 6 years ago • age over 6 years

FPGA-Design-Flow-using-Vivado

40

65

updated almost 6 years ago • age almost 7 years

HTML68.3%

C26.6%

C++3.4%

Tcl0.9%

Scala0.8%

High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS

38

25

updated almost 6 years ago • age almost 7 years

HTML50.5%

VHDL44.5%

C2.3%

Tcl1.7%

C++1.0%

17

9

updated almost 5 years ago • age almost 6 years

V77.4%

Jupyter Notebook14.8%

Tcl6.3%

SystemVerilog0.8%

VHDL0.7%

Xilinx-OpenHW-Contest

6

2

updated about 7 years ago • age about 7 years

Verilog76.6%

C13.4%

HTML5.9%

JavaScript2.4%

Tcl1.6%

dnndk3.0-pynqz2

4

2

updated almost 6 years ago • age about 6 years

Python55.2%

C++30.7%

Shell8.0%

Makefile6.1%

0

0

updated almost 6 years ago • age almost 6 years

C#78.1%

TeX10.7%

Python6.9%

C++3.6%

ShaderLab0.6%

0

0

updated over 6 years ago • age over 6 years

Tcl54.3%

Jupyter Notebook31.9%

Python13.8%

Contributions

2019
AlphaTest_V1.0
1 PR +62-32
0
1