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Profile age: over 4 years
Updated 6 days ago
0 followers • 0 following
Repositories
sfal-vsd
5
2
updated about 1 year ago • age over 1 year
Verilog
97.8%
Tcl
1.6%
HCL
0.4%
SystemVerilog
0.2%
TL-Verilog
0.1%
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