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hkust-zhiyao
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@hkust-zhiyao
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Profile age: about 2 years
Updated 4 days ago
100 followers • 0 following
Repositories
RTL-Coder
223
25
updated 8 months ago • age almost 2 years
Python
100.0%
RTLLM
130
34
updated 11 months ago • age about 2 years
Verilog
96.2%
Makefile
2.9%
Python
0.9%
MasterRTL
54
10
updated 4 months ago • age almost 2 years
Verilog
93.3%
Python
6.7%
Makefile
0.0%
AssertLLM
38
5
updated 11 months ago • age over 1 year
Verilog
84.3%
VHDL
6.9%
C
5.9%
Stata
1.7%
Java
1.2%
RTL-Timer
32
2
updated 4 months ago • age over 1 year
Verilog
99.7%
Python
0.3%
Tcl
0.0%
CircuitFusion
23
1
updated 6 months ago • age 6 months
Python
86.3%
Verilog
13.6%
Makefile
0.1%
APPLE
18
0
updated almost 2 years ago • age almost 2 years
Python
100.0%
PANDA
16
1
updated almost 2 years ago • age almost 2 years
Python
100.0%
NetTAG
16
0
updated about 1 month ago • age 6 months
Python
99.9%
Makefile
0.1%
SpecLLM
15
3
updated over 1 year ago • age over 1 year
Verilog
100.0%
Show more - 10 of 21 shown
Contributions
