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enjoy-digital
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🇫🇷 France
EnjoyDigital
Profile age: over 13 years
Updated 13 days ago
1,447 followers • 0 following
Contacts
florent@enjoy-digital.fr
http://www.enjoy-digital.fr
Organizations
Repositories
litex
3,554
651
3
updated 17 days ago • age almost 10 years
C
51.8%
Python
45.2%
Assembly
1.5%
SystemVerilog
1.3%
Makefile
0.3%
litepcie
593
136
updated 17 days ago • age about 10 years
Python
57.3%
Verilog
28.0%
C
14.4%
Makefile
0.2%
Shell
0.2%
litedram
444
129
updated 22 days ago • age over 10 years
Python
98.5%
C
0.8%
Jinja
0.4%
CSS
0.1%
Verilog
0.1%
liteeth
263
97
updated 22 days ago • age about 10 years
Python
98.3%
Lua
1.7%
usb3_pipe
233
37
updated over 3 years ago • age about 6 years
Verilog
63.9%
Python
30.5%
C
2.9%
SystemVerilog
2.7%
litescope
190
44
updated 22 days ago • age about 10 years
Python
100.0%
pcie_screamer
182
34
updated over 2 years ago • age over 9 years
C
75.2%
Shell
12.8%
Makefile
6.2%
Python
4.5%
M4
1.3%
litesata
150
34
updated 8 days ago • age about 10 years
Python
95.9%
C
4.1%
litex_m2sdr
150
24
updated 8 days ago • age over 1 year
C
69.9%
Python
20.5%
C++
8.8%
Makefile
0.4%
CMake
0.4%
litesdcard
127
37
updated 15 days ago • age about 8 years
Python
61.2%
Verilog
34.1%
SystemVerilog
4.7%
Show more - 10 of 42 shown
Contributions
2024
openFPGALoader
3 PRs
+16
-3
C++
1,442
307
22
litex-boards
3 PRs
+115
-27
Python
439
333
HectaScope
1 PR
+184
-676
Python
5
2
2023
learn-fpga
1 PR
+2
-2
C++
2,987
290
openFPGALoader
3 PRs
+157
-81
C++
1,442
307
22
2022
neorv32
1 PR
+4
-5
VHDL
1,879
285
45
litex-boards
2 PRs
+1,770
-1,473
Python
439
333
corescore
1 PR
+122
-0
Verilog
164
44
Raptor
1 PR
+66
-0
Verilog
87
25
IP_Catalog
2 PRs
+1,165
-4,015
Verilog
16
12
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