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dineshannayya
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Dinesh Annayya
@dineshannayya
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Profile age: about 11 years
Updated about 12 hours ago
80 followers • 0 following
Repositories
riscduino
156
28
updated about 1 year ago • age about 4 years
Tcl
40.5%
SystemVerilog
24.8%
Verilog
22.7%
Makefile
6.2%
C
5.7%
yifive_r0
21
4
updated over 2 years ago • age over 4 years
Verilog
94.0%
SystemVerilog
3.9%
Tcl
1.4%
C
0.5%
Makefile
0.2%
usb1_host
14
5
updated about 4 years ago • age about 4 years
Verilog
80.0%
SystemVerilog
19.6%
Forth
0.3%
riscduino_dcore
13
5
updated about 1 year ago • age over 3 years
Tcl
39.4%
SystemVerilog
23.6%
Verilog
23.5%
Makefile
7.2%
C
6.3%
riscduino_qcore
8
5
updated almost 2 years ago • age over 3 years
Tcl
43.4%
SystemVerilog
23.3%
Verilog
21.9%
Makefile
6.0%
C
5.4%
qspim
7
1
updated about 1 year ago • age about 4 years
SystemVerilog
53.5%
Verilog
35.7%
Tcl
9.8%
Makefile
0.9%
Forth
0.1%
qspis
6
3
updated over 2 years ago • age over 2 years
SystemVerilog
100.0%
logic_bist
5
2
updated over 3 years ago • age almost 4 years
Verilog
94.6%
SystemVerilog
2.5%
Tcl
1.3%
C++
1.3%
Makefile
0.3%
fpu
5
3
updated almost 3 years ago • age over 3 years
SystemVerilog
62.9%
Tcl
16.5%
C
7.6%
Verilog
7.3%
Makefile
5.7%
yifive
5
4
updated over 1 year ago • age about 4 years
Verilog
95.8%
SystemVerilog
3.2%
C
0.5%
Tcl
0.4%
Makefile
0.2%
Show more - 10 of 11 shown
Contributions
2023
library-registry
1 PR
+1
-0
328
2,125
2022
OpenLane
2 PRs
+11
-11
Python
1,582
401
