Rankings
Badges
/
cxlisme
Rankings
Badges
Overview
Ranks
Repositories
Languages
@cxlisme
Refresh
Open GitHub
null
Profile age: almost 4 years
Updated 7 days ago
11 followers • 1 following
Repositories
FPGA-proj
229
49
updated over 3 years ago • age almost 4 years
VHDL
95.5%
Verilog
3.2%
V
0.9%
Shell
0.3%
SystemVerilog
0.1%
Contributions
