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cxlisme
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@cxlisme
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Open GitHub
null
Profile age: over 3 years
Updated 12 days ago
11 followers • 1 following
Repositories
FPGA-proj
229
48
updated over 3 years ago • age over 3 years
VHDL
95.5%
Verilog
3.2%
V
0.9%
Shell
0.3%
SystemVerilog
0.1%
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