R. Timothy Edwards

@RTimothyEdwards

Open GitHub

Poolesville, Maryland

Open Circuit Design

Profile age: over 10 years

Updated 5 days ago

534 followers • 0 following

Contacts

http://opencircuitdesign.com/~tim/

Repositories

magic

566

123

232

updated 9 days ago • age over 6 years

C92.1%

Tcl2.5%

Shell2.2%

TeX1.9%

Perl1.3%

open_pdks

355

102

updated 8 days ago • age about 5 years

Python64.6%

Tcl22.3%

Makefile6.2%

Verilog5.9%

Shell0.9%

qflow

217

updated 11 months ago • age over 6 years

C51.2%

Tcl18.4%

Shell15.7%

SourcePawn8.9%

Verilog5.8%

XCircuit

123

updated 6 months ago • age over 6 years

C84.8%

Tcl5.9%

Shell4.2%

Makefile4.1%

Roff1.1%

netgen

122

updated 17 days ago • age over 6 years

C79.5%

Shell11.2%

Python5.0%

Perl2.6%

Tcl1.7%

qrouter

updated 6 months ago • age over 6 years

C79.6%

Shell19.1%

Tcl0.9%

Makefile0.4%

irsim

updated 6 months ago • age over 6 years

C77.3%

Shell17.3%

Tcl3.5%

Makefile1.3%

PostScript0.6%

capiche

updated 5 months ago • age over 2 years

Python100.0%

tutorial_layout

updated over 2 years ago • age over 2 years

Shell100.0%

sky130_ef_ip__opamp

updated about 1 year ago • age over 1 year

Verilog75.8%

Tcl24.2%

Contributions

2025
IHP-Open-PDK
2 PRs +787-375
HTML
607
108
sscs-chipathon-2025
2 PRs +28-2
Jupyter Notebook
66
48
skywater-pdk-libs-sky130_fd_io
2 PRs +128-99
Verilog
1
0
sky130_ef_ip__adc3v_12bit
1 PR +1-1
Verilog
0
0
1
frigate_analog
1 PR +111-4
Verilog
0
0
2024
cace
~31 PRs +39-7
Python
51
15
skywater-pdk-libs-sky130_fd_pr
~12 PRs +4-14
Python
10
5
skywater-pdk-libs-sky130_fd_sc_hd
3 PRs +349,969-1,243,178
Verilog
4
8
sky130_cw_ip
3 PRs +33,267-6,996
SourcePawn
3
1
sky130_icrg_ip__ulpcomp
2 PRs +6,471-588
Tcl
2
1

R. Timothy Edwards