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Kyp069
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Kyp
@Kyp069
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Open GitHub
🇪🇸 Spain
Profile age: about 9 years
Updated 1 day ago
33 followers • 14 following
Repositories
ep
12
7
1
updated over 1 year ago • age over 2 years
Verilog
47.8%
VHDL
37.4%
SystemVerilog
12.2%
Tcl
2.5%
zx48
10
5
2
updated over 4 years ago • age over 4 years
Verilog
57.5%
VHDL
36.4%
SystemVerilog
6.1%
zx48-MiSTer
7
5
3
updated about 4 years ago • age over 4 years
Verilog
48.1%
VHDL
32.6%
SystemVerilog
16.4%
Tcl
2.8%
Batchfile
0.1%
zx.old
7
6
updated almost 4 years ago • age almost 4 years
Verilog
68.3%
VHDL
20.8%
Shell
3.9%
Tcl
3.8%
SystemVerilog
3.2%
zxp3
6
5
1
updated 8 months ago • age over 2 years
VHDL
56.2%
Verilog
37.5%
SystemVerilog
4.9%
Tcl
1.4%
zx128
5
3
1
updated over 4 years ago • age over 4 years
Verilog
57.6%
VHDL
36.3%
SystemVerilog
6.0%
zx
4
2
1
updated almost 2 years ago • age about 3 years
VHDL
50.0%
Verilog
47.5%
SystemVerilog
1.3%
Tcl
1.3%
lynx.zxuno
1
0
updated over 4 years ago • age about 5 years
VHDL
77.4%
Verilog
22.6%
demistify
0
2
updated over 3 years ago • age almost 4 years
VHDL
68.6%
Verilog
25.3%
SystemVerilog
3.2%
HTML
2.9%
Contributions
2022
zxuno
2 PRs
+318
-76
VHDL
13
8
