Filippo Marini

@FilMarini

Open GitHub

🇮🇹 Padova, Italy

INFN Padova

Profile age: almost 6 years

Updated 28 days ago

3 followers • 8 following

Repositories

FPGA_CDR_core

updated almost 4 years ago • age over 5 years

VHDL75.6%

TeX13.0%

Makefile6.6%

Tcl4.9%

blue-rdma

updated about 1 year ago • age over 1 year

Bluespec93.6%

Python3.1%

Shell2.1%

Tcl1.0%

Makefile0.2%

bleak

updated 12 months ago • age 12 months

Python99.2%

Java0.8%

blue-udp

updated over 1 year ago • age over 1 year

Bluespec47.7%

Verilog35.5%

Tcl7.2%

Python5.5%

Makefile4.2%

firmware-hls

Archived

updated over 2 years ago • age over 3 years

C++58.6%

Python14.6%

C9.4%

Tcl9.2%

VHDL8.1%

Contributions

2025
ruckus
1 PR +6-1
Tcl
78
38
123
2024
surf
3 PRs +1,411-476
VHDL
403
77
165
ruckus
1 PR +264-21
Tcl
78
38
123
2023
ruckus
1 PR +16-3
Tcl
78
38
123
vhdl-ext
1 PR +8-2
Emacs Lisp
35
5
14
firmware-hls
2 PRs +9,362-25
Tcl
17
24
2022
ruckus
1 PR +231-1
Tcl
78
38
123
CM_FPGA_FW
1 PR +66-2
VHDL
0
0
2021
ghdl-language-server
1 PR +10-9
Common Lisp
100
10
2020
ReliabilityCalc
1 PR +397-0
C++
4
0
5