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AngeloJacobo
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Angelo Jacobo
@AngeloJacobo
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Open GitHub
🇵🇭 Bulacan, Philippines
Profile age: about 4 years
Updated 5 days ago
194 followers • 4 following
Contacts
jacobo.angeloECE@gmail.com
https://www.linkedin.com/in/angelo-jacobo
Repositories
UberDDR3
384
54
updated 4 months ago • age over 2 years
Verilog
58.6%
SystemVerilog
22.1%
Tcl
16.2%
Makefile
1.7%
Shell
1.4%
FPGA_Book_Experiments
148
24
updated about 4 years ago • age about 4 years
Verilog
100.0%
RISC-V
111
9
7
updated almost 2 years ago • age over 3 years
Verilog
42.5%
Assembly
25.9%
C
24.2%
Shell
6.4%
Tcl
0.9%
FPGA_OV7670_Camera_Interface
67
9
updated almost 4 years ago • age about 4 years
Verilog
100.0%
OpenLANE-Sky130-Physical-Design-Workshop
65
17
updated about 3 years ago • age about 3 years
FPGA_RealTime_and_Static_Sobel_Edge_Detection
64
4
updated almost 4 years ago • age about 4 years
Verilog
99.6%
Python
0.4%
DDR3-Notes
39
9
updated over 2 years ago • age over 2 years
FPGA_SDRAM_Controller
28
5
updated about 4 years ago • age about 4 years
Verilog
100.0%
ULX3S_FPGA_Camera_Streaming
23
1
updated almost 4 years ago • age almost 4 years
Verilog
97.6%
Makefile
2.4%
ULX3S_FPGA_Sobel_Edge_Detection_OV7670
18
2
updated almost 4 years ago • age almost 4 years
Verilog
98.0%
Makefile
2.0%
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Contributions
